1–16
Chapter 1: Overview for the Arria V Device Family
Enhanced Configuration and Configuration via Protocol
Enhanced Configuration and Configuration via Protocol
Arria V devices support 3.3-V programming voltage and the following configuration
modes:
■
■
■
■
■
■
active serial (AS)
passive serial (PS)
fast passive parallel (FPP)
CvP
Configuration via HPS
configuration through JTAG
You can configure Arria V devices through PCIe using CvP instead of an external
flash or ROM. The CvP mode offers the fastest configuration rate and flexibility with
the easy-to-use PCIe hard IP block interface. The Arria V CvP implementation
conforms to the PCIe 100-ms power-up-to-active time requirement.
f
For more information regarding CvP, refer to the Configuration via Protocol (CvP)
Implementation in Altera FPGAs User Guide.
Table 1–11 lists the configuration modes that Arria V devices support.
Table 1–11. Configuration Modes and Features for Arria V Devices
Maximum
Clock Rate
(MHz)
Maximum
Data Rate Decompression
(Mbps)
Remote
System
Update
Design
Security
Partial
Reconfiguration
Mode
Data Width (Bit)
AS
PS
1, 4
1
100
125
—
v
v
v
v
v
—
—
125
—
Parallel
flash loader
FPP
CvP
HPS
8, 16
125
—
—
—
—
33
v
v
v
—
v
v
v
—
16-bit only
x1, x2, x4, x8 (1)
v
v
v
—
Parallel
32
1
125
33
flash loader
JTAG
—
Note to Table 1–11:
(1) Number of lanes instead of bits.
Power Management
Arria V devices leverage FPGA architectural features and process technology
advancements to reduce the total device core power consumption by as much as 50%
when compared with Stratix IV devices at the same performance level.
Additionally, Arria V devices have a number of hard IP blocks that not only reduce
logic resources but also deliver substantial power savings when compared with soft
implementations. The list includes PCIe Gen1 and Gen2, XAUI, GbE, SRIO, GPON
and CPRI protocols. The hard IP blocks consume up to 25% less power than
equivalent soft implementations.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation