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5AGTMB1D631I4N 参数 Datasheet PDF下载

5AGTMB1D631I4N图片预览
型号: 5AGTMB1D631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–12  
Chapter 1: Overview for the Arria V Device Family  
ALM  
ALM  
Arria V devices use a 28-nm ALM as the basic building block of the device fabric. The  
ALM shown in Figure 1–3 uses an 8-input fracturable look-up table (LUT) with four  
dedicated registers to help improve timing closure in register-rich designs and  
achieve an even higher design packing capability than previous generations.  
You can configure up to 25% of the ALMs in Arria V devices as distributed MLABs.  
For more information, refer to “Embedded Memory” on page 1–14.  
Figure 1–3. ALM for Arria V Devices  
Reg  
1
Full  
Adder  
2
3
4
5
6
7
Reg  
Reg  
Adaptive  
LUT  
8
Full  
Adder  
Reg  
Variable-Precision DSP Block  
Arria V devices feature a variable-precision DSP block that you can configure to  
support signal processing with precision ranging from 9 x 9, 18 x 19, and 27 x 27 bits  
natively.  
You can independently configure each DSP block during compilation as a triple 9 x 9,  
a dual 18 x 19 multiply, or a single 27 x 27. With a dedicated 64-bit cascade bus, you  
can cascade multiple variable-precision DSP blocks to implement even higher  
precision DSP functions efficiently.  
The variable precision DSP block also supports these features:  
64-bit accumulator that is the largest in the industry,  
Double accumulator  
Hard pre-adder that is available in both 18- and 27-bit modes  
Cascaded output adders for efficient systolic FIR filters  
Dynamic coefficients  
18-bit internal coefficient register banks  
Enhanced independent multiplier operation  
Efficient support for single floating point arithmetic  
Inferability of all modes by the Altera Complete Design Suite  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
February 2012 Altera Corporation  
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