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5AGTMB1D631I4N 参数 Datasheet PDF下载

5AGTMB1D631I4N图片预览
型号: 5AGTMB1D631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Overview for the Arria V Device Family  
1–5  
Arria V Family Plan  
Table 1–3. Maximum Resource Counts for Arria V GT, SX, and ST Devices—Preliminary  
Arria V GT Device  
Arria V SX Device  
Arria V ST Device  
Feature  
5AGTD3  
5AGTD7  
190,240  
504  
5ASXB3  
5ASXB5  
174,340  
462  
5ASTD3  
5ASTD5  
174,340  
462  
ALMs  
LE (K)  
136,880  
362  
1,726  
2,098  
17,260  
1,045  
2,090  
12  
132,075  
350  
132,075  
350  
M10K memory blocks  
MLAB memory (Kb)  
Block memory (Kb)  
Variable-precision DSP blocks  
18 x 19 multipliers  
FPGA Fractional PLLs (1)  
HPS PLLs (1)  
2,414  
2,906  
24,140  
1,156  
2,312  
16  
1,729  
2,014  
17,288  
809  
2,282  
2,658  
22,820  
1,068  
2,186  
TBD  
TBD  
528  
1,729  
2,014  
17,288  
809  
2,282  
2,658  
22,820  
1,068  
2,186  
TBD  
TBD  
528  
1,618  
TBD  
TBD  
528  
1,618  
TBD  
TBD  
528  
FPGA GPIO  
704  
704  
HPS I/O  
216  
216  
216  
216  
LVDS TX (2)  
LVDS RX (2)  
160  
176  
2
160  
120  
120  
120  
120  
176  
120  
120  
120  
120  
PCIe hard IP blocks  
Hard memory controllers  
HPS memory controllers  
2
2
2
2
2
4
4
3
3
3
3
1
1
1
1
ARM Cortex–A9 MPCore  
processor  
Dual-core  
Dual-core  
Dual-core  
Dual-core  
Notes to Table 1–3:  
(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs,  
when not used by the transceiver I/O, can be used as a general-purpose fractional PLL.  
(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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