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5AGTFA1D627C4N 参数 Datasheet PDF下载

5AGTFA1D627C4N图片预览
型号: 5AGTFA1D627C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–50  
Chapter 2: Device Datasheet for Arria V Devices  
Glossary  
Table 2–48. Glossary Table (Part 3 of 4)  
Letter  
Subject  
Definitions  
Timing Diagram—the period of time during which the data must be valid in order to capture  
it correctly. The setup and hold times determine the ideal strobe position in the sampling  
window, as shown:  
Sampling  
Bit Time  
window (SW)  
Sampling Window  
(SW)  
RSKM  
RSKM  
0.5 x TCCS  
0.5 x TCCS  
The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal  
values. The AC values indicate the voltage levels at which the receiver must meet its timing  
specifications. The DC values indicate the voltage levels at which the final logic state of the  
receiver is unambiguously defined. After the receiver input has crossed the AC value, the  
receiver changes to the new logic state.  
The new logic state is then maintained as long as the input stays beyond the AC threshold.  
This approach is intended to provide predictable receiver timing in the presence of input  
waveform ringing, as shown:  
S
Single-Ended Voltage Referenced I/O Standard  
Single-ended  
voltage  
VCCIO  
referenced I/O  
standard  
VOH  
VIH  
(
)
AC  
VIH(DC)  
VREF  
VIL(DC)  
VIL(AC  
)
VOL  
VSS  
tC  
High-speed receiver/transmitter input and output clock period.  
The timing difference between the fastest and slowest output edges, including the tCO  
variation and clock skew, across channels driven by the same PLL. The clock is included in  
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).  
TCCS (channel-  
to-channel-skew)  
High-speed I/O block—Duty cycle on high-speed transmitter output clock.  
Timing Unit Interval (TUI)  
tDUTY  
The timing budget allowed for skew, propagation delays, and the data sampling window.  
T
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)  
tFALL  
Signal high-to-low transition time (80–20%)  
Cycle-to-cycle jitter tolerance on the PLL clock input  
Period jitter on the GPIO driven by a PLL  
Period jitter on the dedicated clock output driven by a PLL  
Signal low-to-high transition time (20–80%)  
tINCCJ  
tOUTPJ_IO  
tOUTPJ_DC  
tRISE  
U
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
February 2012 Altera Corporation  
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