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5AGTFA1D627C4N 参数 Datasheet PDF下载

5AGTFA1D627C4N图片预览
型号: 5AGTFA1D627C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–49  
Glossary  
Table 2–48. Glossary Table (Part 2 of 4)  
Letter  
Subject  
Definitions  
High-speed I/O block—Deserialization factor (width of parallel data bus).  
JTAG Timing Specifications:  
J
TMS  
TDI  
tJCP  
J
JTAG Timing  
Specifications  
tJCH  
t JCL  
tJPH  
tJPSU  
TCK  
TDO  
tJPXZ  
tJPZX  
tJPCO  
K
L
M
N
O
(1)  
Diagram of PLL Specifications  
CLKOUT Pins  
fOUT_EXT  
Switchover  
4
CLK  
fIN  
fINPFD  
N
GCLK  
RCLK  
Counters  
C0..C17  
fVCO  
VCO  
fOUT  
PFD  
CP  
LF  
Core Clock  
PLL  
Specifications  
P
Delta Sigma  
Modulator  
Key  
External Feedback  
Reconfigurable in User Mode  
Note:  
(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.  
Q
R
RL  
Receiver differential input discrete resistor (external to the Arria V device).  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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