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5AGTFA1D627C4N 参数 Datasheet PDF下载

5AGTFA1D627C4N图片预览
型号: 5AGTFA1D627C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–44  
Chapter 2: Device Datasheet for Arria V Devices  
Configuration Specification  
Table 2–42 lists the internal clock frequency specification for the AS configuration  
scheme.  
Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary (1), (2)  
Minimum  
Typical  
7.9  
Maximum  
12.5  
Unit  
MHz  
MHz  
MHz  
MHz  
5.3  
10.6  
21.3  
15.7  
31.4  
62.9  
25.0  
50.0  
42.6  
100.0  
Notes to Table 2–42:  
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.  
(2) The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.  
PS Configuration Timing  
Figure 2–8 shows the timing waveform for a passive serial (PS) configuration when  
using a MAX II device or microprocessor as an external host.  
(1)  
Figure 2–8. PS Configuration Timing Waveform  
tCF2ST1  
tCFG  
tCF2CK  
nCONFIG  
nSTATUS (2)  
tSTATUS  
tCF2ST0  
(6)  
tCLK  
CONF_DONE (3)  
t
CH tCL  
tCF2CD  
tST2CK  
(4)  
(5)  
DCLK  
tDH  
Bit 2 Bit 3  
Bit n  
Bit 0 Bit 1  
DATA0  
tDSU  
High-Z  
User I/O  
User Mode  
INIT_DONE (7)  
tCD2UM  
Notes to Figure 2–8:  
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG  
, nSTATUS, and CONF_DONEare at logic high levels. When  
nCONFIGis pulled low, a reconfiguration cycle begins.  
(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.  
(3) After power up, before and during configuration, CONF_DONEis low.  
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.  
(5) DATA0is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins  
Option.  
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device  
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization  
and enter user mode.  
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.  
Arria V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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