2–40
Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Table 2–39 lists the timing parameters for Arria V devices for FPP configuration when
the DCLK-to-DATA[]ratio is 1.
(1)
Table 2–39. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is 1—Preliminary
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIGlow pulse width
2
268
—
—
µs
µs
µs
µs
µs
(2)
nSTATUSlow pulse width
1506
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
(3)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
1506
1506
2
—
—
DATA[]setup time before rising edge on
DCLK
5.5
—
ns
DATA[]hold time after rising edge on DCLK
DCLKhigh time
0
—
—
ns
ns
tDH
0.45 x 1/fMAX
tCH
DCLKlow time
0.45 x 1/fMAX
—
ns
tCL
DCLKperiod
1/fMAX
—
ns
tCLK
fMAX
tR
DCLKfrequency (FPP x8/ x16)
Input rise time
—
125
40
MHz
ns
—
Input fall time
—
175
40
ns
tF
(4)
CONF_DONEhigh to user mode
437
—
µs
tCD2UM
tCD2CU
tCD2UMC
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLKperiod
—
t
CD2CU + (Tinit x CLKUSR
CONF_DONEhigh to user mode with CLKUSR
option on
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 2–39:
(1) Use these timing parameters when the DCLK-to-DATA[]ratio is 1. To find the DCLK-to-DATA[]ratio for your system, refer Table 2–38 on
page 2–38.
(2) You can obtain this value if you do not delay configuration by extending the nCONFIGor the nSTATUSlow pulse width.
(3) You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
