AS7C32098A
®
Read waveform 2 (CE, OE, UB, LB controlled)5,7,8
tRC
Address
tAA
OE
tOHZ
tOE
tOH
tOLZ
CE
tACE
tCLZ
tCHZ
LB, UB
tBA
tBHZ
tBLZ
DataOUT
Data valid
Write cycle (over the operating range)9
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit Note
t
t
t
10
7
–
–
–
–
–
–
–
–
–
–
5
–
–
12
8
–
–
–
–
–
–
–
–
15
10
10
0
–
–
–
–
–
–
–
–
–
–
7
–
–
20
12
12
0
–
–
–
–
–
–
–
–
–
–
9
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip enable (CE) to write end
Address setup to write end
Address setup time
7
8
t
0
0
AS
t
t
7
8
10
15
0
12
20
0
Write pulse width (OE = High)
Write pulse width (OE = Low)
Write recovery time
WP1
WP2
10
0
12
0
t
WR
t
0
0
0
0
Address hold from end of write
Data valid to write end
AH
t
5
6
7
9
DW
t
0
0
–
6
–
–
0
0
3,4
3,4
3,4
3,4
Data hold time
DH
WZ
t
t
0
0
0
0
Write enable to output in High-Z
Output active from write end
Byte enable Low to write end
3
3
3
3
OW
t
7
8
10
12
BW
2/24/05,v. 1.0
Alliance Semiconductor
P. 5 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
