AS7C32098A
February 2005
Preliminary Information
®
3.3 V 128K × 16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 131,072 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
- 28.8 mW /max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
Logic block diagram
Pin arrangement for TSOP 2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
1
2
3
4
5
6
44
43
42
41
A16
A15
A14
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
A0
A1
A2
V
CC
1024 × 128 × 16
A3
GND
A4
40
39
38
37
36
35
34
33
32
31
30
Array
(2,097,152)
A6
A7
A8
7
A12
A13
8
9
I/O1–I/O8
I/O9–I/O16
I/O
buffer
Control circuit
10
V
11
12
13
14
15
CC
Column decoder
WE
GND
I/O5
I/O6
I/O7
V
CC
I/O12
I/O11
I/O10
UB
OE
LB
CE
I/O8
WE
A5
A6
A7
A8
A9
16
17
18
19
20
21
22
29
I/O9
NC
28
27
26
25
24
23
A13
A12
A11
A10
NC
Selection guide
–10
10
4
–12
–15
15
6
–20
20
7
Unit
Maximum address access time
12
5
ns
ns
Maximum output enable access time
Industrial
180
170
8
160
150
8
140
130
8
110
100
8
mA
mA
mA
Maximum operating current
Commercial
Maximum CMOS standby current
2/24/05, v. 1.0
Alliance Semiconductor
P. 1 of 10
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