March 2004
AS7C1025B
®
5V 128K X 8 CMOS SRAM (Center power and ground)
Features
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
Pin arrangement
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
Logic block diagram
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
V
A16
CC
A0
1
32
31
30
A15
A14
A13
OE
I/O7
A1
A2
A3
CE
I/O0
I/O1
2
3
4
5
6
7
GND
29
28
27
26
25
24
23
22
21
20
19
Input buffer
I/O6
GND
A0
A1
V
8
CC
I/O7
I/O0
V
GND
I/O2
I/O3
WE
A4
A5
A6
A7
9
10
CC
A2
I/O5
512 x 256 x 8
Array
(1,048,576)
A3
I/O4
A12
A11
A10
11
A4
A5
A6
A7
A8
12
13
14
15
16
A9
A8
18
17
WE
Control
circuit
Column decoder
OE
CE
Selection guide
-10
10
5
-12
12
6
-15
-20
20
8
Unit
ns
Maximum address access time
Maximum output enable access time
Maximum operating current
15
7
ns
110
10
100
10
90
10
80
10
mA
mA
Maximum CMOS standby current
3/26/04, v. 1.3
Alliance Semiconductor
P. 1 of 9
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