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AS6VA25616-TI 参数 Datasheet PDF下载

AS6VA25616-TI图片预览
型号: AS6VA25616-TI
PDF下载: 下载PDF文件 查看货源
内容描述: 2.7V至3.3V 256K ×16 Intelliwatt低功耗CMOS SRAM有一个芯片使能 [2.7V to 3.3V 256K x 16 Intelliwatt low-power CMOS SRAM with one chip enable]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 175 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS6VA25616  
®
Data retention characteristics (over the operating range)13,5  
Parameter  
Symbol  
Test conditions  
Min  
1.2V  
Max  
3.3  
4
Unit  
V
V
for data retention  
V
V
CC  
= 1.2V  
CC  
DR  
CS V – 0.1V or  
CC  
Data retention current  
I
mA  
ns  
CCDR  
UB = LB = > V – 0.1V  
CC  
Chip deselect to data retention time  
Operation recovery time  
t
0
CDR  
V
V – 0.1V or  
IN  
CC  
t
V
0.1V  
IN  
tRC  
ns  
R
Data retention waveform  
Data retention mode  
VDR 1.2V  
VCC  
VCC  
VCC  
tCDR  
tR  
VDR  
VIH  
VIH  
CS  
AC test loads and waveforms  
Thevenin equivalent:  
RTH  
R1  
R1  
VCC  
VCC  
OUTPUT  
V
OUTPUT  
OUTPUT  
30 pF  
5 pF  
ALL INPUT PULSES  
V
CC Typ  
R2  
R2  
90%  
10%  
90%  
10%  
INCLUDING  
JIG AND  
INCLUDING  
JIG AND  
SCOPE  
< 5 ns  
(c)  
GND  
(a)  
SCOPE  
(b)  
Parameters  
V
= 3.0V  
V
= 2.5V  
V
= 2.0V  
Unit  
CC  
CC  
CC  
R1  
R2  
1105  
16670  
15294  
Ohms  
Ohms  
Ohms  
Volts  
1550  
645  
15380  
8000  
1.2V  
11300  
6500  
R
TH  
V
1.75V  
0.85V  
TH  
Notes  
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification.  
This parameter is sampled, but not 100% tested.  
For test conditions, see AC Test Conditions.  
t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.  
This parameter is guaranteed, but not tested.  
WE is HIGH for read cycle.  
CS and OE are LOW for read cycle.  
Address valid prior to or coincident with CS transition LOW.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 N/A.  
13 1.2V data retention applies to commercial and industrial temperature range operations.  
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.  
6
ALLIANCE SEMICONDUCTOR  
10/6/00