February 2007
AS6C62256
®
32K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
2.7
0.7*Vcc
- 0.5
- 1
TYP. *5
3.3
MAX.
5.5
VCC+0.5
0.6
UNIT
PARAMETER
Supply Voltage
VCC
V
V
V
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
-
-
-
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
Output Disabled
IOL = 2mA
1
A
µ
ILO
- 1
-
1
A
µ
Output High Voltage
Output Low Voltage
VOH IOH = -1mA
VOL
2.4
-
3.0
-
-
V
V
0.4
Cycle time = Min.
CE# = VIL , II/O = 0mA
ICC
15
3
45
-55
-
-
mA
.
Average Operating
Power supply Current
Cycle time = 1 s
µ
ICC1
≦
10
3
mA
mA
CE# 0.2V and II/O = 0mA
other pins at 0.2V or VCC-0.2V
CE# = VIH
ISB
-
-
-
1
1
1
Standby Power
Supply Current
*4
-C
50
A
µ
A
µ
ISB1
CE# ≧VCC - 0.2V
-I
*4
80
Notes: C = Commercial Temperature I = Industrial Temperature
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10 A for special request
µ
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25ºC
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
02/FEB/07, v1.0
Alliance Memory Inc.
Page 3 of 12
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
