AS5LC2M16
&
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
TH
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
90%
V
Typ
R2
CC
R2
90%
10%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
GND
(a)
SCOPE
(b)
(c)
Parameters
VCC = 2.7V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
992
1842
645
Ω
Ω
RTH
VTH
Ω
1.755V
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS1 is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS1 and OE are LOW for read cycle.
Address valid prior to or coincident with CS1 transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS1 or WE must be HIGH during address transitions. Either CS1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
14 Memory cell data hold invalid.
2/15/02; V.0.9.6
Alliance Semiconductor
P. 8 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
