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AS4LC4M4F1-60JC 参数 Datasheet PDF下载

AS4LC4M4F1-60JC图片预览
型号: AS4LC4M4F1-60JC
PDF下载: 下载PDF文件 查看货源
内容描述: 4M × 4 CMOS DRAM(快速页面), 3.3V系列 [4M×4 CMOS DRAM (Fast Page) 3.3V Family]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 14 页 / 269 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS4LC4M4F1  
®
Functional description  
The AS4LC4M4F1 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 4,194,304  
words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed,  
extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as  
main memory in PC, workstation, router and switch applications.  
This device features a high speed page-mode operation where read and write operations within a single row (or page) can be executed at  
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the  
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of  
column addresses prior to CAS assertion.  
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:  
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.  
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with  
previous valid data.  
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.  
Outputs are high-impedence (OE and WE are don't care).  
• Normal read or write cycles refresh the row being accessed.  
• Self-refresh cycles  
The AS4LC4M4F1 is available in the standard 24/26-pin plastic SOJ. TSOP 24/26-pin availability is to be determined. The AS4LC4M4F1  
operates with a single power supply of 3.3V 0.3V and provides TTL compatible inputs and outputs.  
Logic block diagram for 2K refresh  
Data  
I/O  
buffers  
VCC  
Column decoder  
Sense amp  
GND  
I/O0 to I/O3  
RAS clock  
generator  
RAS  
CAS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
2048 × 2048 × 4  
Array  
CAS clock  
generator  
(16,777,216)  
A9  
A10  
Substrate bias  
generator  
WE clock  
generator  
WE  
Recommended operating conditions  
Parameter  
Symbol  
VCC  
Min  
3.0  
0.0  
2.0  
–0.5†  
0
Nominal  
Max  
Unit  
V
3.3  
0.0  
3.6  
0.0  
Supply voltage  
Input voltage  
GND  
VIH  
V
VCC+0.5V  
0.8  
V
VIL  
V
Commercial  
Industrial  
70  
Ambient operating temperature  
TA  
°C  
-40  
85  
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.  
IL  
5/16/01; v.1.0 Restored  
Alliance Semiconductor  
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