AS4LC4M16S0
AS4LC16M4S0
®
Device operation
Command
Pin settings
Description
The following sequence must be performed prior to normal
operation.
1. Apply power, start clock, and assert CKE and DQM high. All other
signals are NOP.
2. After power-up, pause for a minimum of 200µs.
CKE/ DQM = high; all others NOP.
Power up
3. Precharge both banks.
4. Perform Mode Register Set command to initialize mode register.
5. Perform a minimum of 8 auto refresh cycles to stabilize internal
circuitry.
(Steps 4 and 5 may be interchanged.)
The mode register stores the user selected opcode for the SDRAM
operating modes. The CAS latency, burst length, burst type, test mode
and other vendor specific functions are selected/ programmed during
the Mode Register Set command cycle. The default setting of the
mode register is not defined after power-up. The power-up and mode
register set cycle must be executed prior to normal SDRAM operation.
Refer to the Mode Register Set table and timing for details.
CS = RAS = CAS = WE = low;
A0~A11 = opcode
Mode register set
The SDRAM performs a “no operation” (NOP) when RAS, CAS, and
WE = high. Since the NOP performs no operation, it may be used as
a wait state in performing normal SDRAM functions. The SDRAM is
deselected when CS is high. CS high disables the command decoder
such that RAS, CAS, WE and address inputs are ignored. Device
deselection is also considered a NOP.
Device deselect and no
operation
CS = high
The SDRAM is configured with four internal banks. Use the Bank
Activate command to select a row in one of the idle banks. Initiate
a read or write operation after tRCD(min) from the time of bank
activation.
CS = RAS = low; CAS = WE =
high; A0~A10 = row address;
BA0~BA1 = bank select
Bank activation
Burst read
Use the Burst Read command to access a consecutive burst of data
from an active row in an active bank. Burst read can be initiated on
any column address of an active row. The burst length, sequence and
latency are determined by the mode register setting. The first output
data appears after the CAS latency from the read command. The
output goes into a high impedance state at the end of the burst
(BL = 1,2,4,8) unless a new burst read is initiated to form a gapless
output data stream. Terminate the burst with a burst stop command,
precharge command to the same bank or another burst read/ write.
CS = CAS = A10 = low; RAS =
WE = high; BA0~BA1 = bank
select, A0~A8 = column
address; (A9 = don’t care for
8M×8; A8,A9 = don’t care for
4M×16)
Use the Burst Write command to write data into the SDRAM on
CS = CAS = WE = A10 = low; consecutive clock cycles to adjacent column addresses. The burst
RAS = high; A0~A9 = column length and addressing mode is determined by the mode register
address; (A9 = don’t care for opcode. Input the initial write address in the same clock cycle as the
8M×8; A8,A9 = don’t care for Burst Write command. Terminate the burst with a burst stop
Burst write
4M×16)
command, precharge command to the same bank or another burst
read/ write.
Use DQM to mask input and output data on a cycle-by-cycle basis. It
disables the output buffers in a read operation and masks input data in
a write operation. The output data is invalid 2 clocks after DQM
assertion (2 clock latency). Input data is masked on the same clock as
DQM assertion (0 clock latency).
UDQM/ LDQM (×16),
DQM (×8) operation
10
ALLIANCE SEMICONDUCTOR
7/ 5/ 00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
