128M DDR1 -AS4C8M16D1
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23(5$7,1*ꢀ&855(17ꢐꢀOne bank; Active-Precharge; t =t (min);
ꢒꢆ
ꢒꢅꢀ
0D[ꢁꢀ
6\PEROꢀ
8QLWꢀ
RC RC
60
55
t
=t (min); DQ,DM and DQS inputs changing once per clock cycle;
CK CK
IDD0
mA
Address and control inputs changing once every two clock cycles.
23(5$7,1*ꢀ&855(17ꢀꢐꢀOne bank; Active-Read-Precharge; BL=4;
75
5
65
5
t
=t (min); t =t (min); lout=0mA; Address and control inputs changing
mA
mA
RC RC
CK CK
IDD1
once per clock cycle
35(&+$5*(ꢀ32:(5ꢒ'2:1ꢀ67$1'%<ꢀ&855(17ꢐ All banks idle;
power-down mode; t =t (min); CKE=LOW
IDD2P
CK CK
,'/(ꢀ67$1'/<ꢀ&855(17ꢀꢐ CKE = HIGH;
=HIGH(DESELECT); All
CS
banks idle; t =t (min); Address and control inputs changing once per
30
17
40
30
17
40
mA
mA
mA
IDD2N
IDD3P
IDD3N
CK CK
clock cycle; V =V
for DQ, DQS and DM
REF
IN
$&7,9(ꢀ32:(5ꢒ'2:1ꢀ67$1'%<ꢀ&855(17ꢀꢐ one bank active; power-
down mode; CKE=LOW; t =t (min)
CK CK
$&7,9(ꢀ67$1'%<ꢀ&855(17ꢀꢐ
=HIGH;CKE=HIGH; one bank active ;
CS
=t (max);t =t (min);Address and control inputs changing once per
t
RC RC
CK CK
clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle
23(5$7,1*ꢀ&855(17ꢀ%8567ꢀ5($'ꢀꢐꢀBL=2; READS; Continuous burst;
120
120
100
100
one bank active; Address and control inputs changing once per clock cycle;
mA
mA
IDD4R
IDD4W
t
=t (min); lout=0mA;50% of data changing on every transfer
CK CK
23(5$7,1*ꢀ&855(17ꢀ%8567ꢀ:ULWHꢀꢐꢀBL=2; WRITES; Continuous
Burst ;one bank active; address and control inputs changing once per clock
cycle; t =t (min); DQ,DQS,and DM changing twice per clock cycle; 50%
CK CK
of data changing on every transfer
80
2
70
2
mA
mA
$872ꢀ5()5(6+ꢀ&855(17ꢀꢐ t =t
(min); t =t (min)
IDD5
IDD6
RC RFC
CK CK
ꢀ
6(/)ꢀ5()5(6+ꢀ&855(17ꢐꢀSelf Refresh Mode ; CKE 0.2V;t =t (min)
CK CK
%8567ꢀ23(5$7,1*ꢀ&855(17ꢀꢆꢀEDQNꢀRSHUDWLRQꢐꢀ
Four bank interleaving READs; BL=4; with Auto Precharge; t =t (min);
RC RC
160
140
IDD7
mA
t
=t (min); Address and control inputs change only during Active, READ ,
CK CK
or WRITE command
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CK
CK
tRCD
READ
AP
READ
AP
READ
AP
READ
AP
ACT
ACT
ACT
ACT
ACT
COMMAND
ADDRESS
...pattern repeats...
Bank 1
Row e
Bank 0
Row d
Bank 2
Row f
Bank 1
Col e
Bank 3
Row g
Bank 0
Row h
Bank 3
Col c
Bank 0
Col d
Bank 2
Col f
CL=3
DQS
DQ
D0 a
D0 a D0 a D0 b
D0 a
D0 b D0 b D0 b
D0 d D0 d
D0 e
D0 e
D0 f
D0 f
D0 c D0 c D0 c D0 c
D0 d D0 d D0 e
D0 e
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
