AS4C64M8D2
Figure 26. Burst write followed by burst read:
RL=5 (AL=2, CL=3, WL=4, tWTR=2, BL=4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK#
CK
Write to Read = CL-1+BL/2+tWTR
NOP NOP NOP
Post CAS#
READ A
NOP
NOP
NOP
NOP
NOP
CKE
DQS#
DQS
DQS
DQS#
WL = RL-1 = 4
AL=2
CL=3
RL=5
>=tWTR
DQ
DOUT A0
DNA0 DNA1 DNA2 DNA3
NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + tWTR].
This tWTR is not a write recovery time (tWR) but the time required to transfer the 4 bit write data from the input buffer into
sense amplifiers in the array. tWTR is defined in the timing parameter table of this standard.
Figure 27. Seamless burst write operation RL=5, WL=4, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Post CAS#
Write A
Post CAS#
Write B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
DQS#
DQS
DQS
DQS#
WL = RL-1 = 4
DQ
DNA0 DNA1 DNA2 DNA3 DNB0 DNB1 DNB2 DNB3
NOTE : The seamless burst write operation is supported by enabling a write command every other clock for
BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
Confidential
42
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
