AS4C4M32S
Figure 13. Write to Precharge
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
Precharge
BANK(S)
NOP
NOP
WRITE
Activate
ROW
NOP
NOP
NOP
COMMAND
ADDRESS
BANK
COL n
tWR
DIN
N+1
DIN
N
DQ
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
7
Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
Figure 14. Burst Write with Auto-Precharge
(Burst Length = 2)
T5 T6 T7
T0
T1
T2
T3
T4
T8
T9
CLK
Bank A
Activate
Bank A
Activate
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL
DIN A0
DIN A1
DQ
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
8
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. Two clock cycles are required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
Alliance Memory Confidential
11
Rev. 3.0 May. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
