AS4C4M32S
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A WRITE B
COMMAND
DQ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
READ B
NOP
CAS# latency=2
tCK2, DQ
DOUT B0 DOUT B1 DOUT B2 DOUT B3
CAS# latency=3
tCK3, DQ
DIN A0
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ at least one clock cycle before
the Read data appears on the outputs to avoid data contention
Don’t Care
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
Alliance Memory Confidential
10
Rev. 3.0 May. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
