AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Test Mode Field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 11. Test Mode
A8
0
A7
0
Test Mode
Normal mode
DLL Reset
1
0
X
1
Test mode
(BA0, BA1)
•
Table 12. MRS/EMRS
BA1
RFU
RFU
BA0
0
A11 ~ A0
MRS Cycle
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power up
for proper operation. The extended mode register is written by asserting low on
,
,
, and WE . (the
CS RAS CAS
device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE
should be High)The state of A0 ~ A11 and BA1 are written in the mode register in the same cycle
as
,
,
, and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high
CK RAS CAS
prior to writing into the extended mode register. A1 is used for setting driver strength. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
Table 13. Extended Mode Register Bitmap
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Field
0
1
RFU must be set to “0”
DS DLL Extended Mode Register
A0
DLL
BA0
0
Mode
MRS
A1
0
Drive Strength
Full
0
1
Enable
Disable
1
EMRS
1
Reserved
Confidential
- 11/64 -
Rev.1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
