4Mx16 DDR1-AS4C4M16D1A
ꢀPin Descriptions
Table 2. Pin Details
Symbol
CK,
Type
Description
Input
Differential Clock: CK and
are differential clock inputs. All address and control
CK
CK
input signals are sampled on the crossing of the positive edge of CK and negative
edge of . Input and output data is referenced to the crossing of CK and (both
CK
directions of the crossing)
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
A0-A11
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10 defining
Auto Precharge).
Input
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the command
CS
CS
decoder. All commands are masked when
is sampled HIGH.
provides for
CS
CS
external bank selection on systems with multiple banks. It is considered part of the
command code.
Row Address Strobe: The
signal defines the operation commands in
signals and is latched at the positive edges of
RAS
RAS
and
WE
conjunction with the
CAS
CK. When
and
are asserted "LOW" and
is asserted "HIGH," either
CAS
CS
RAS
the BankActivate command or the Precharge command is selected by the
WE
signal. When the
is asserted "HIGH," the BankActivate command is selected and
WE
the bank designated by BA is turned on to the active state. When the
is asserted
WE
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in
CAS
CAS
signals and is latched at the positive edges of
conjunction with the
and
WE
RAS
CK. When
is held "HIGH" and
is asserted "LOW," the column access is
CS
"LOW." Then, the Read or Write command is selected by
RAS
started by asserting
CAS
"HIGH " or LOW"."
asserting
WE
Write Enable: The
signal defines the operation commands in conjunction with
WE
WE
signals and is latched at the positive edges of CK. The
CAS
the
and
input
WE
RAS
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
UDQS
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input / Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
Output negative edges of LDQS & UDQS. The I/Os are byte-maskable during Writes.
VDD
Supply
Power Supply: +2.5V ±0.2V
Confidential
- 5/54 -
Rev.1.1 July 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
