AS4C256M16D3
Figure 68. Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
COMMAND
ADDRESS
ODTLoff
ODTH4
ODT
RTT
ODTLon
tAON
tADC
(min)
(min)
RTT_NOM
tADC
tAON
(max)
(max)
DQS, DQS#
DQ
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
TRANSITIONING DATA
Don't Care
Figure 69. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for duration of 6 clock cycles
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
NOP
NOP
WRS8
VALID
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
ODTLcnw
ODTH8
ODTLoff
ODTLon
ODT
RTT
tAON
tAOF
(min)
(min)
RTT_WR
tADC
(max)
tAOF
ODTLcwn8
WL
(max)
DQS, DQS#
DQ
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
NOTES:
Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
TRANSITIONING DATA
Don't Care
Confidential
78
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
