AS4C256M16D3
Figure 65. Synchronous ODT Timing Example
(AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
ODT
AL = 3
AL = 3
CWL - 2
ODTH4, min
ODTLoff = CWL + AL - 2
ODTLon = CWL + AL - 2
tAOF
tAON
(min)
(min)
DRAM_RTT
RTT_NOM
tAON
tAOF
(max)
(max)
TRANSITIONING DATA
Don't Care
Figure 66. Synchronous ODT example with BL = 4, WL = 7
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
CKE
ODTH4min
NOP
ODTH4
NOP
ODTH4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
COMMAND
ODT
ODTLoff = WL - 2
ODTLon = WL - 2
ODTLoff = WL - 2
ODTLon = WL - 2
tAOF
tAON
tAOF
(min)
(min)
(min)
tAON
(max)
(min)
RTT_NOM
DRAM_RTT
tAON
tAON
(max)
tAOF
tAOF
(max)
(max)
TRANSITIONING DATA
Don't Care
Figure 67. Dynamic ODT Behavior with ODT being asserted before and after the write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
VALID
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
ODTH4
ODTLoff
ODTH4
ODT
RTT
ODTLon
ODTLcwn4
tAON
tADC
(min)
tAOF
(min)
(min)
tADC
(min)
RTT_NOM
RTT_WR
RTT_NOM
tADC
(max)
tAOF
(max)
tAON
tADC
(max)
(max)
ODTLcnw
DQS, DQS#
DQ
Din
n
Din
n+1
Din
n+2
Din
n+3
WL
TRANSITIONING DATA
Don't Care
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
Confidential
77
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
