AS4C256M16D3
Timing Waveforms
Figure 25. MPR Readout of predefined pattern,BL8 fixed burst order, single readout
CK#
T0
Ta
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Td
CK
tMPRR
tMOD
PREA
MRS
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
MRS
MRS
VALID
COMMAND
BA
Notes 1
tRP
tMOD
3
0
VALID
3
VALID
0
0
A[1:0]
A[2]
Notes 2
1
0
Notes 2
00
VALID
00
A[9:3]
A10, AP
A[11]
1
0
0
VALID
VALID
0
0
0
0
VALID
VALID
0
0
A12, BC#
A[14:13]
DQS, DQS#
DQ
RL
NOTES:
1. RD with BL8 either by MRS or OTF.
TIME BREAK
Don't Care
2. Memory Controller must drive 0 on A[2:0].
Figure 26. MPR Readout of predefined pattern,BL8 fixed burst order, back to back radout
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK#
CK
tMPRR
tMOD
PREA
MRS
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
VALID
COMMAND
BA
Notes 1
Notes 1
tRP
tMOD
tCCD
3
0
VALID
VALID
3
VALID
0
0
0
A[1:0]
A[2]
Notes 2
Notes 2
1
0
0
Notes 2
Notes 2
A[9:3]
00
VALID
VALID
00
A10, AP
A[11]
0
0
VALID
VALID
VALID
VALID
0
0
1
0
0
VALID
VALID
0
0
A12, BC#
A[14:13]
Notes 1
Notes 1
VALID
VALID
RL
DQS, DQS#
DQ
RL
NOTES:
1. RD with BL8 either by MRS or OTF.
2. Memory Controller must drive 0 on A[2:0].
TIME BREAK
Don't Care
Confidential
60
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
