AS4C256M16D3
- Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the
tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max
and the first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input
signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time
might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a
valid input signal is still required to complete the transition and reach VIH/IL(ac).
Table 39. ADD/CMD Setup and Hold Base-Values for 1V/ns
Symbol
Reference
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
-12 BCN/BIN Unit
tIS(base) AC175
tIS(base) AC150
tIH(base) DC100
45
ps
ps
ps
170
120
NOTE 1: (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
NOTE 2: The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference
point [(175 mv - 150 mV) / 1 V/ns].
Table 40. Derating values DDR3-1333/1600 tIS/tIH – (AC175)
△t , △t derating in [ps] AC/DC based AC175 Threshold -> V (ac)=V
(dc)+175mV, V (ac)=V
(dc)-175mV
REF
IS
IH
IH
REF
IL
CK, CK# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns 1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
58
42
8
△tIS
△tIH
66
50
16
12
6
△tIS
△tIH
74
58
24
20
14
8
△tIS
△tIH
84
68
34
30
24
18
8
△tIS
△tIH
100
84
CMD
/ADD
Slew
Rate
V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
50
88
59
0
50
88
59
0
50
96
67
8
104
75
16
14
10
5
112
83
24
22
18
13
7
120
91
32
30
26
21
15
-2
128
99
40
38
34
29
23
5
34
34
34
0
0
0
50
-2
-4
-2
-4
-2
-4
6
4
46
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
2
-2
40
-11
-17
-35
-62
-11
-17
-35
-62
-11
-17
-35
-62
-3
-9
-27
-54
-8
0
34
-18
-32
-52
-1
-10
-24
-44
-2
24
-19
-46
-11
-38
-16
-36
-6
10
-30
-26
-22
-10
Table 41. Derating values DDR3-1333/1600 tIS/tIH – (AC150)
△t , △t derating in [ps] AC/DC based Alternate AC150 Threshold -> V (ac)=V
(dc)+150mV, V (ac)=V
(dc)-150mV
REF
IS
IH
IH
REF
IL
CK, CK# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns 1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
58
42
8
△tIS
△tIH
66
50
16
12
6
△tIS
△tIH
74
58
24
20
14
8
△tIS
△tIH
84
68
34
30
24
18
8
△tIS
115
90
40
40
40
40
39
30
15
△tIH
100
84
CMD
/ADD
Slew
Rate
V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
50
75
50
0
50
75
50
0
50
83
58
8
91
66
16
16
16
16
15
6
99
74
24
24
24
24
23
14
-1
107
82
32
32
32
32
31
22
7
34
34
34
0
0
0
50
0
-4
0
-4
0
-4
8
4
46
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
8
-2
40
0
0
0
8
-8
0
34
-1
-10
-25
-1
-10
-25
-1
-10
-25
7
-18
-32
-52
-10
-24
-44
-2
24
-2
-17
-16
-36
-6
10
-9
-26
-10
Confidential
58
Rev. 3.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
