AS4C256K16E0
®
Notes
1
2
3
I
CC1
, I
CC3
, I
CC4
, and I
CC6
depend on cycle rate.
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
An initial pause of 200
µs
is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume t
T
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V
IL
(min)
≥
GND and V
IH
(max)
≤
V
CC
.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
Assumes three state test load (5 pF and a 380
Ω
Thevenin equivalent).
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
WS
≥
t
WS
(min) and t
WH
≥
t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min) and t
AWD
≥
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of t
CAA
or t
CAC
or t
CAP
.
t
ASC
≥
t
CP
to achieve t
PC
(min) and t
CAP
(max) values.
These parameters are sampled and not 100% tested.
4
5
6
7
8
9
10
11
12
13
14
15
Key to switching waveform
Undefined/don’t care
Rising input
Falling input
Read cycle waveform
t
RC
t
RAS
t
RCD
t
RSH
t
RP
RAS
t
CSH
t
CRP
t
ASC
t
RCS
t
CAH
t
CAS
UCAS,
LCAS
t
RAD
t
ASR
t
RAH
t
AR
t
RAL
Address
Row Address
Col Address
t
RRH
t
RCH
WE
t
ROH
OE
t
RAC
t
AA
t
OEA
t
CAC
t
CLZ
t
OEZ
t
OFF
I/O
Data Out
4/11/01; v.1.1
Alliance Semiconductor
7 of 24
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
