AS4C16M16SA
Figure 22. Power on Sequence and Auto Refresh
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Minimum for 2 Refresh Cycles are required
Is reguired
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9
A11-A12
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Command
Any
Command
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Inputs must be
Mode Register
Set Command
Stable for
200μs
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
Confidential
24
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
