AS3V2M16
&
Functional description
The AS3V2M16 is a low-power single transister (IT) CMOS 33,554,432-bit Pseudo Static Random Access Memory (PSRAM)
device organized as 2,097,152 × 16 bits. It is designed for memory applications where slow data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/ 70/ 85 ns are ideal for low-power applications.
The device can be put into deep power down mode with ZZ low and the power consumption at 3.3V is reduced to 33 µW. N o t e
that in deep power down mode the memory cell will not retain its data.
The device can also be put into standby mode when deselected (CS and ZZ high or UB and LB high with ZZ high). The input/
output pins (I/ O0 through I/ O15) are placed in a high-impedance state when: deselected ( CS is high , or UB and LB are high),
outputs are disabled (OE High), UB and LB are disabled (UB, LB High), during a write operation ( CS is low and WE Low), or in
power down mode(ZZ is low).
Writing to the device is accomplished by taking Chip Select (CS) Low and Write Enable (WE) input Low. If Byte Low Enable (LB)
is Low, then data from I/ O pins (I/ O0 through I/ O7), is written into the location specified on the address pins (A0 through
A20). If Byte High Enable (UB) is Low, then data from I/ O pins (I/ O8 through I/ O15) is written into the location specified on
the address pins (A0 through A20). To avoid bus contention, external devices should drive I/ O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Select (CS) and Output Enable (OE) Low while forcing the Write Enable (WE)
High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins will appear on I/ O0 to I/ O7.
If Byte High Enable (UB) is Low, then data from memory will appear on I/ O8 to I/ O15.
These devices provide multiple power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/ O0–I/ O7, and UB controls the higher bits, I/ O8–I/ O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–
Max
VCC + 0.5
VCC + 0.5
1.0
Unit
V
Voltage on VCC relative to V
V
tIN
SS
Voltage on any I/ O pin relative to GND
V
V
tI/ O
Power dissipation
PD
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
+150
°C
°C
mA
+125
20
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
10/ 17/ 02, V. 0.9.9
Alliance Semiconductor
P. 2 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
