AS29F010
AS29F011
FUNCTIONAL DESCRIPTION
The AS29F010 and AS29F011 are high performance 1 megabit
byte wide Flash EEPROM memories. They are organized as
131,072 words × 8 bits, and divided into four sectors of 32K bytes
each. Each sector is separately erased and programmed without
affecting data in the other sectors. All program, erase, and verify
operations are 5-volt only, and require no external 12V supply pin.
All required features for in-system programmability are provided.
four write cycles to be executed. Address and data are latched
internally during all write, erase, and verify operations, and an
internal timer terminates each command. The chip has a typical
timer period of 200 µs for all commands but Erase, which has a
typical period of 800 ms. Under nominal conditions, a sector can
be completely programmed and verified in less than 12 seconds.
To program, erase, and verify a sector typically takes less than 18
seconds.
The AS29F010 and AS29F011 provide high performance with a
maximum access time of 70, 90, 120, or 150 ns. Chip Enable (CE),
Output Enable (OE), and Write Enable (WE) pins allow easy
interface with the system bus. The AS29F011 is functionally
identical to the AS29F010 except for an additional input RP,
which controls a deep power-down function. When the RP pin is
Data protection is provided by a low-V
lockout and by error
CC
checking in the Write State Machine. Data-bar polling and Toggle
Bit modes are used to show that the chip is executing a command
when the AS29F010 or AS29F011 is read during a write or erase
operation. After Erase or Program commands, Verify-1 and
Verify-0 command modes ensure sufficient margin for reliable
operation. (See command summary on page 5.)
pulled low (less than V the AS29F011 is disabled, reducing
IL)
power consumption to virtually zero. The AS29F011 recovers in
<2 µs when RP is pulled high.
The AS29F010 and AS29F011 are packaged in 32-pin DIP, PLCC
and TSOP packages with JEDEC standard pinouts for one megabit
Flash memories.
Program, erase, and verify operations are controlled with an on-
chip command register using a JEDEC standard Write State
Machine approach to enter commands. Each command requires
ARRAY ARCHITECTURE AND DATA POLARITY
The array consists of 128K (131,072) bytes divided into four
sectors of 32K bytes each. Addresses A15 and A16 select the four
sectors:
all bytes in a 32K sector to the erased state FFh, or all bits set to 1.
Each sector is erased individually with no effect on the other
sectors.
Address Pins
Function
Sector
Address Range
A0–A5
CA: Column addresses 00–3Fh
RA: Row addresses 000–1FFh
SA: Sector addresses 0–3h
0
1
2
3
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
A6–A14
A15–A16
The AS29F010 and AS29F011 are shipped in the erased state with
all bits set to 1. Programmed bits are set to 0. Data is programmed
into the array one byte at a time. Within a programmed byte, any
bit that remains set to 1 can be programmed to 0 later, but all
programmed bits remain set to 0 until the sector is erased and
verified using the Sector Erase and Verify algorithm. Erase returns
OPERATING MODES
The AS29F010 and AS29F011 are controlled by a Write State
Machine (WSM) that interprets and executes commands. At
power-up the WSM is reset to normal mode, which allows the chip
to operate as a ROM. Once a command is initiated by writing data
into the I/O pins with the WE pin, the WSM enters the command
mode and keeps the chip powered up until the command is
finished. After the command is terminated by the internal timer,
the WSM returns to the normal mode and the chip may be read as a
ROM.
The RP pin of the AS29F011 overrides all other inputs. Any
operation in progress is interrupted when the RP pin is pulled low.
2
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
