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A2040C-08SR 参数 Datasheet PDF下载

A2040C-08SR图片预览
型号: A2040C-08SR
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 9 页 / 492 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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December 2003  
rev 1.0  
P2040C  
Block Diagram  
SSON#  
VDD  
SR0 SR1 MRA  
Modulation  
PLL  
CLKIN  
Frequency  
Divider  
Output  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
ModOUT  
VSS  
Pin Configuration  
1
2
3
4
8
7
6
5
CLKIN  
VDD  
SR0  
MRA  
P2040C  
ModOUT  
SSON#  
SR1  
VSS  
Pin Description  
Pin  
Pin#  
Type  
Description  
Name  
1
2
CLKIN  
I
I
External reference frequency input. Connect to externally generated reference signal.  
Digital logic input used to select modulation rate. This pin has an internal pull-up  
MRA  
resistor.  
Digital logic input used to select Spreading Range. This pin has an internal pull-up  
3
4
SR1  
VSS  
I
resistor.  
P
Ground to entire chip. Connect to system ground.  
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread  
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal  
pull-low resistor.  
5
SSON#  
I
6
7
8
ModOUT  
SR0  
O
I
Spread spectrum clock output.  
Digital logic input used to select Spreading Range. This pin has an internal pull-up  
resistor.  
VDD  
P
Power supply for the entire chip (3.3V)  
LCD Panel EMI Reduction IC  
2 of 9  
Notice: The information in this document is subject to change without notice.