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AK5365VQ 参数 Datasheet PDF下载

AK5365VQ图片预览
型号: AK5365VQ
PDF下载: 下载PDF文件 查看货源
内容描述: 与SELETOR / PGA / ALCL 24位ADC 96KHZ [24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl]
分类和应用:
文件页数/大小: 41 页 / 286 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI
[AK5365
]
DC CHARACTERISTICS
(Ta=−40
85°C; AVDD=4.75
5.25V; DVDD=3.0
5.25V)
Parameter
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout=−400µA)
VOH
Low-Level Output Voltage
(Except SDA pin : Iout=400µA)
VOL
(SDA pin : Iout=3mA)
VOL
Input Leakage Current
Iin
min
70%DVDD
-
DVDD-0.5
-
-
-
typ
-
-
-
-
-
-
Max
-
30%DVDD
-
0.5
0.4
±10
Units
V
V
V
V
V
µA
SWITCHING CHARACTERISTICS
(Ta=−40
85°C; AVDD=4.75
5.25V; DVDD=3.0
5.25V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Duty Cycle
fCLK
tCLKL
tCLKH
fsn
fsd
Slave mode
Master mode
8.192
0.4/fCLK
0.4/fCLK
32
48
45
50
typ
max
24.576
Units
MHz
ns
ns
kHz
kHz
%
%
48
96
55
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 16)
BICK “↑” to LRCK Edge
(Note 16)
LRCK to SDTO (MSB) (Except I
2
S mode)
BICK “↓” to SDTO
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
fBCK
dBCK
tMBLR
tBSD
160
65
65
30
30
35
35
64fs
50
−20
−20
20
35
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
MS0164-E-01
-9-
2002/08