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AK5357VT 参数 Datasheet PDF下载

AK5357VT图片预览
型号: AK5357VT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位96kHz的ツヒADC [24Bit 96kHz ΔΣ ADC]
分类和应用:
文件页数/大小: 20 页 / 294 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK5357]
SWITCHING CHARACTERISTICS
(Ta=Tmin
Tmax; VA=VD=2.7
5.5V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
1.024
fCLK
Frequency
0.4/fCLK
tCLKL
Pulse Width Low
0.4/fCLK
tCLKH
Pulse Width High
LRCK Frequency
fs
4
Duty Cycle
Slave mode
45
Master mode
Audio Interface Timing
Slave mode
160
tSCK
SCLK Period
65
tSCKL
SCLK Pulse Width Low
65
tSCKH
Pulse Width High
30
tLRSH
LRCK Edge to SCLK “↑”
30
tSHLR
SCLK “↑” to LRCK Edge
2
tLRS
LRCK to SDTO (MSB) (Except I S mode)
tSSD
SCLK “↓” to SDTO
Master mode
fSCK
SCLK Frequency
dSCK
SCLK Duty
−20
tMSLR
SCLK “↓” to LRCK
−20
tSSD
SCLK “↓” to SDTO
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid at Slave Mode (Note
PDN “↑” to SDTO valid at Master Mode (Note
tPD
tPDV
tPDV
150
typ
max
36.864
Units
MHz
ns
ns
kHz
%
%
96
55
50
35
35
64fs
50
20
35
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
1/fs
1/fs
4132
4129
Note 11. SCLK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK5357 can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0294-E-03
-8-
2009/03