[AK5358A]
OPERATION OVERVIEW
■ System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5358A may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5358A in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
256fs
384fs
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
32kHz
44.1kHz
48kHz
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
12.288MHz
16.9344MHz
18.432MHz
36.864MHz
96kHz
Table 1. System Clock Example
Mode CKS2 CKS1 CKS0 Input Level
Master/Slave
Slave
MCLK
SCLK
256/384fs (8k≤fs≤96k)
512/768fs (8k≤fs≤48k)
Reserved
256fs (8k≤fs≤96k)
512fs (8k≤fs≤48k)
256/385fs(∼ 96kHz)
512/768fs(∼ 48kHz)
Reserved
≥ 48fs or 32fs
(Note 15)
0
L
L
L
CMOS
1
2
3
L
L
L
L
H
H
H
L
H
CMOS
CMOS
Master
Master
64fs
64fs
≥ 48fs or 32fs
(Note 15)
4
H
L
L
TTL
Slave
5
6
7
H
H
H
L
H
H
H
L
H
CMOS
CMOS
Master
Master
64fs
64fs
384fs (8k≤fs≤96k)
768fs (8k≤fs≤48k)
Table 2. Operation Mode Select
Note 15. SDTO outputs 16bit data at SCLK=32fs.
MS0511-E-01
2007/04
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