ASAHI KASEI
[AK5353]
PIN/FUNCTION
No.
1
2
3
Pin Name
AINR
AINL
VREF
I/O
I
I
O
Description
Rch Analog Input Pin
Lch Analog Input Pin
Voltage Reference Output Pin
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 4.7uF.
Common Voltage Output Pin
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 4.7uF.
Analog Ground Pin, 0V
Analog Power Supply Pin, +2.7∼+5.5V
Digital Power Supply Pin, +2.7∼+5.5V
Digital Ground Pin, 0V
Serial Data Output Pin
Data bits are presented MSB first, in 2 s complement format.
This pin is L in the power-down mode.
Left/Right Channel Select Pin
The fs clock is input to this pin.
Master Clock Input Pin
Serial Data Input Pin
Output data is clocked out on the falling edge of SCLK.
Power-Down Pin
When L , the circuit is in power-down mode.
The AK5353 should always be reset upon power-up.
Serial Interface Format Pin
L : MSB justified, H : I
2
S
Digital Input Level Select Pin
L : CMOS level (VA,VD=2.7∼5.5V), H : TTL level (VA,VD=4.5∼5.5V)
Test Pin (Internal pull-down pin)
This pin should be left floating.
4
VCOM
O
5
6
7
8
9
AGND
VA
VD
DGND
SDTO
-
-
-
-
O
10
11
12
13
LRCK
MCLK
SCLK
PDN
I
I
I
I
14
15
16
DIF
TTL
TST
I
I
I
Note: All input pins except pull-down pins should not be left floating.
M0067-E-00
-3-
1999/06
AKM [ ASAHI KASEI MICROSYSTEMS ]
