[AK4706]
2. Audio Block
■ System Clock
The external clocks required to operate the DAC section of AK4706 are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 4 illustrates
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC section of AK4706 is in the normal operating mode (STBY bit = “0” and DAPD bit = “0”). If these clocks are not
provided, the AK4706 may draw excess current because the device utilizes dynamically refreshed logic internally. The
DAC section of AK4706 should be reset by STBY bit = “0” after threse clocks are provided. If the external clocks are not
present, place the AK4706 in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4706
remains in power-down mode until MCLK and LRCK are input.
LRCK
fs
MCLK
BICK
64fs
256fs
384fs
32.0kHz
44.1kHz
48.0kHz
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
16.9344MHz
18.4320MHz
2.0480MHz
2.8224MHz
3.0720MHz
Table 4. System clock example
■ Audio Serial Interface Format (00H: D5-D4)
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial
mode as shown in Table 5. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode DIF1 DIF0 SDTI Format
BICK
≥32fs
≥36fs
≥48fs
≥48fs or
32fs
Figure
Figure 4
Figure 4
Figure 5
0
1
2
0
0
1
0
1
0
16bit LSB Justified
18bit LSB Justified
24bit MSB Justified
3
1
1
24bit I2S Compatible
Figure 6
(default)
Table 5. Audio Data Formats
MS0507-E-01
2010/09
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
