[AK4706]
■ DAC Power-down Mode
The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit =“1”, the
zero-cross detection and offset calibration does not work.
DAPD bit (00H D2): DAC power-down bit.
“1”: DAC power-down. Analog-input mode.
#52 pin: MCLK Æ Unused pin. This pin should be open.
#53 pin: BICK Æ DACR. Rch analog input.
#54 pin: SDTI Æ Unused pin. This pin should be open.
#55 pin: LRCK Æ DACL. Lch analog input.
“0”: DAC operation. (default)
■ Standby Mode
When the AUTO bit = MUTE bit = “0” and the STBY bit = “1”, the AK4706 is forced into TV-VCR loop through mode.
In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of VCROUTL/R
are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values themselves are NOT
changed by STBY bit = “1”.
STBY bit (00H D0): Standby bit.
“1”: Standby mode. (default)
“0”: Normal operation.
■ Mute Mode (Bias-off Mode. 00H: D1)
When the MUTE bit = “1”, the bias voltage on the audio output goes to GND level. Bringing MUTE bit to “0” changes
this bias voltage smoothly from GND to VP/2 by 2sec(typ.). This removes the huge click noise related the sudden change
of bias voltage at power-on. The change of MUTE bit from “1” to “0” also makes smooth transient from VP/2 to GND by
2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off.
MUTE bit: Bias-off bit.
“1”: Set the audio bias to GND. (default)
“0”: Normal operation
■ Normal Operation Mode
To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bit and STBY bit to “0”. The DAC is in
power-down mode until MCLK and LRCK are input. The AK4706 is in power-down mode until MCLK and LRCK are
input. The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin.
MS0507-E-01
2010/09
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
