ASAHI KASEI
[AK4702EQ]
Mode Control Interface
I2C-bus Control Mode
The AK4702 supports the standard-mode I2C-bus (max: 100kHz). Then AK4702 doesn’t support the fast-mode I2C-bus
system (max: 400kHz).
1. WRITE Operations
Figure 8 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 14). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4702, the AK4702 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 15). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4702. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 10). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 11). The AK4702 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 14).
The AK4702 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4702
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 08H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 16) except for the START and the STOP
condition.
S
S
T
O
P
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8. Data transfer sequence at the I2C-bus mode
0
0
0
0
1
0
0
0
1
R/W
A0
Figure 9. The first byte
0
A4
A3
A2
A1
D1
Figure 10. The second byte
D7
D6
D5
D4
D3
D2
D0
Figure 11. Byte structure after the second byte
MS0424-E-00
2005/09
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
