ASAHI KASEI
[AK4702EQ]
The Figure 7 shows an example of the system timing at the power-down and power-up by PDN pin.
PDN pin
“Stand-by“
“Mute”
“Stand-by“
MUTE bit
STBY bit
“1” (default)
“1” (default)
“1”
“0”
“1”
“0”
“1”
“0”
don’t care (2)
don’t care
don’t care (2)
don’t care
normal operation
Audio data
Clock in
Data in
“0”
“0”
GD
GD
(1)
(1)
D/A Out
(internal)
TV-Source
select
VCR in
fixed to VCR in(Loop-through)
VCR in
DAC
(default)
(4)
offset calibration
VCR in
VCR in
TV out
(3)
Notes:
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3) Please mute the analog outputs externally if click noise(3) adversely affects the system.
(4) In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUT is switched to
DAC after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”.
Figure 7. Power-down/up sequence example
MS0424-E-00
2005/09
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
