[AK4679]
SDOUT4
GP1
C2 I2CE
Serial Data Output 4 Pin
DSP Programmable output 1 Pin
Control Interface Mode Select Pin for DSP Block “H”: I2CE, “L”: SPI
(SELDO4 bit = “0”)
(SELDO4 bit = “1”)
D2
O
I
Serial Clock Input pin
SPI (I2CE pin = “L”)
SCLK
CAD0
CSN
SCLE
C7
I
Slave Address 0 Input pin
Chip select pin
I2C (I2CE pin = “H”)
SPI (I2CE pin = “L”)
B8
I
Control Interface clock input pin
Serial data output pin
I2C (I2CE pin = “H”)
SPI (I2CE pin = “L”)
SO
O
C5
SDAE
I/O Control Interface input/output acknowledge pin
I2C (I2CE pin = “H”)
SPI (I2CE pin = “L”)
I2C(I2CE pin = “H”)
Serial data input pin
SI
C6
I
CAD1
Slave Address 1 Input pin
E4 TEST
I
Test pin (pull-down resistor) must be connected to VSS4.
Note 2. All input pins must not be allowed to float.
Note 3. I2CE and CAD0/1 pins must be fixed to “L” (VSS4) or “H” (TVDDE).
■ Handling of Unused Pin on the System
The unused input and output pins on the system should be processed appropriately as below.
Classification
Analog
Pin Name
Setting
MPWR1, MPWR2, SPP, SPN, RCP, RCN, HPL,
HPR, ROUT/LON, LOUT/LOP, RIN4, LIN4,
RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-,
RIN1/IN1−, LIN1/IN1+, CPA, CNA, CPB, CNB,
VEE, SPFIL
These pins should be open.
SDTO, SDTOA, SDTOB
These pins should be open.
STO/RDY, SDOUT3/GPO, SDOUT4/GP1
MCKI, SDTI, SDTIA, SDTIB, BICKA, SYNCA,
BICKB, SYNCB
These pins should be connected to VSS2.
Digital
These pins should be connected to VSS2
and M/S bit should be set to “0”.
LRCK, BICK
SYNC1, BCLK1, SDIN3, SDIN4, SYNC3/JX1,
BCLK3/JX0, TEST
These pins should be connected to VSS4
■ Pin States in DSP Power-down Mode
The table below shows pin states when the PDNE pin= “L”.
NO
Pin Name
STO
RDY
I/O
Pin state
Low
G3
O
H1 SDOUT1
D6 SYNC2
F2 BCLK2
C4 SDOUT2
O
O
O
O
SDIN2 data output
SYNC1 data output
BCLK1 data output
SDIN1 data output
SDIN4 data output
SDOUT3
F4
O
GP0
SDOUT4
GP1
SO
SDAE
SDIN3 data output
D2
O
O
Low level (I2CE pin = “L”: SPI)
(I2CE pin = “H” :I2C)
C5
I/O Hi-z
MS1402-E-06
2013/02
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
