[AK4679]
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
SDTIB
L2 L1 L0 L15 L14 L13 L12 L11 L10 L9 L8
L7 L6 L5 L4 L3 L2 LD10 L0 L15 L14
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 R7 R6 R5 R4 R3 R2 RD10 R0 L7 L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
L15 L14 L13 L8 L7 L1 L1 L0 R15 R13 R1 R0
L15 L14
SDTIB
Don’t Care
Don’t Care
L15 L14 L13 L8 L7 L1 L1 L0 R15 D6
R1 R0
L15 L14
L7 L6
(8bit A-Law/μ-Law)
SDTOB
L7 L6 L6
L7 L6 D5
L0 R7 R1 R1 R0
SDTIB
Don’t Care
Don’t Care
L0 R7 D2
R1 R0
L7 L6
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch Data: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 96. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
SDTIB
L2 L1 L0 L15 L14 L13 L12 L11 L10 L9 L8
L7 L6 L5 L4 L3 L2 LD10 L0 L15 L14
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 R7 R6 R5 R4 R3 R2 RD10 R0 L7 L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
L15 L14 L13 L8 L7 L1 L1 L0 R15 R13 R1 R0
L15 L14
SDTIB
Don’t Care
Don’t Care
L15 L14 L13 L8 L7 L1 L1 L0 R15 D6
R1 R0
L15 L14
L7 L6
(8bit A-Law/μ-Law)
SDTOB
L7 L6 L6
L7 L6 D5
L0 R7 R1 R1 R0
SDTIB
Don’t Care
Don’t Care
L0 R7 D2
R1 R0
L7 L6
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch Data: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 97. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “1”)
MS1402-E-06
2013/02
- 128 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
