[AK4675]
Parameter
Symbol
min
typ
max
Units
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
8
tBCK−60
45
-
-
-
48
1/fs − tBCK
55
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period
tLRCKH
Duty
tBCK
tBCKL
tBCKH
1/(64fs)
130
130
-
-
-
1/(32fs)
ns
ns
ns
Pulse Width Low
Pulse Width High
-
-
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
8
tBCK−60
45
-
-
-
48
1/fs − tBCK
55
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
tLRCKH
Duty
Period
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
tBCK
tBCK
tBCKL
tBCKH
-
-
1/(32fs)
1/(64fs)
-
-
-
-
ns
ns
ns
ns
Pulse Width Low
Pulse Width High
0.4 x tBCK
0.4 x tBCK
-
-
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
fCLK
fCLK
fCLK
fCLK
tCLKL
tCLKH
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
-
-
-
-
-
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
384fs
512fs
768fs
1024fs
Pulse Width Low
Pulse Width High
-
ns
LRCK Input Timing
Frequency
256fs/384fs
512fs/768fs
1024fs
fs
fs
fs
8
8
-
-
-
-
-
48
26
kHz
kHz
kHz
ns
8
tBCK−60
45
13
1/fs − tBCK
55
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period
tLRCKH
Duty
%
tBCK
tBCKL
tBCKH
312.5
130
130
-
-
-
-
-
-
ns
ns
ns
Pulse Width Low
Pulse Width High
External Master Mode
MCKI Input Timing
Frequency
256fs
384fs
512fs
768fs
1024fs
fCLK
fCLK
fCLK
fCLK
fCLK
tCLKL
tCLKH
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
-
-
-
-
-
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
Pulse Width Low
Pulse Width High
-
ns
LRCK Output Timing
Frequency
fs
8
-
-
-
48
-
-
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Output Timing
tLRCKH
Duty
tBCK
50
Period
BCKO bit = “0”
BCKO bit = “1”
tBCK
tBCK
dBCK
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
Duty Cycle
MS0963-E-00
2008/05
- 27 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
