[AK4675]
SWITCHING CHARACTERISTICS (CODEC, SRC)
(Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; CL=20pF (except SDA pin) or
400pF (SDA pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
Pulse Width Low
Pulse Width High
MCKO Output Timing
Frequency
fMCK
0.256
-
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz
dMCK
dMCK
40
-
50
33
60
-
%
%
256fs at fs=32kHz
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Output Timing
fs
8
-
-
-
48
-
-
kHz
ns
%
tLRCKH
Duty
tBCK
50
Period
BCKO bit = “0”
BCKO bit = “1”
tBCK
tBCK
dBCK
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
Duty Cycle
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
Pulse Width Low
Pulse Width High
MCKO Output Timing
Frequency
fMCK
0.256
-
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
256fs at fs=32kHz, 29.4kHz
LRCK Input Timing
dMCK
dMCK
40
-
50
33
60
-
%
%
Frequency
fs
8
tBCK−60
45
-
-
-
48
1/fs − tBCK
55
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period
tLRCKH
Duty
tBCK
tBCKL
tBCKH
1/(64fs)
0.4 x tBCK
0.4 x tBCK
-
-
-
1/(32fs)
ns
ns
ns
Pulse Width Low
Pulse Width High
-
-
MS0963-E-00
2008/05
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
