ASAHI KASEI
[AK4665A]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.6 ∼ 3.6V; TVDD=1.6∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
Pulse Width Low
fCLK
tCLKL
tCLKH
2.048
0.4/fCLK
0.4/fCLK
-
-
-
24.576
MHz
ns
ns
-
-
Pulse Width High
LRCK Timing
Frequency
Duty Cycle
fs
Duty
8
45
44.1
48
55
kHz
%
Serial Interface Timing (Note 18)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 19)
BICK “↑” to LRCK Edge (Note 19)
LRCK to SDTO(MSB)
BICK “↓” to SDTO
SDTI Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
325.5
130
130
50
50
-
-
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDTI Setup Time
-
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Power-down & Reset Timing
PDN Pulse Width (Note 20)
PMADC “↑” to SDTO valid (Note 21)
tCSH
tPD
tPDV
150
-
-
-
-
ns
1/fs
2081
Note 18. Refer to “Serial Data Interface”.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. The AK4665A can be reset by bringing PDN= “L” to “H” only upon power up.
Note 21. This is the count of LRCK “↑” from PMADC bit=”1”.
MS0440-E-01
2006/05
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
