[AK4646]
Parameter
Symbol
min
typ
max
Units
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
Duty
fs
Duty
7.35
45
-
-
48
55
kHz
%
BICK Input Timing
Period
tBCK
tBCKL
tBCKH
1/(64fs)
240
240
-
-
-
1/(32fs)
ns
ns
ns
Pulse Width Low
Pulse Width High
-
-
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
Duty
fs
Duty
7.35
45
-
-
48
55
kHz
%
BICK Input Timing
Period
tBCK
tBCK
tBCKL
tBCKH
-
-
1/(32fs)
1/(64fs)
-
-
-
-
ns
ns
ns
ns
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
Pulse Width Low
Pulse Width High
0.4 x tBCK
0.4 x tBCK
-
-
External Slave Mode
MCKI Input Timing
Frequency
256fs
512fs
1024fs
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
-
-
-
-
12.288
13.312
13.312
MHz
MHz
MHz
ns
Pulse Width Low
Pulse Width High
-
-
ns
LRCK Input Timing
Frequency
256fs
512fs
1024fs
fs
fs
fs
7.35
7.35
7.35
45
-
-
-
-
48
26
13
55
kHz
kHz
kHz
%
Duty
Duty
BICK Input Timing
Period
tBCK
tBCKL
tBCKH
312.5
130
130
-
-
-
-
-
-
ns
ns
ns
Pulse Width Low
Pulse Width High
External Master Mode
MCKI Input Timing
Frequency
256fs
512fs
1024fs
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
-
-
-
-
12.288
13.312
13.312
MHz
MHz
MHz
ns
Pulse Width Low
Pulse Width High
LRCK Output Timing
Frequency
-
-
ns
fs
Duty
7.35
-
-
50
48
-
kHz
%
Duty Cycle
BICK Input Timing
Period
BCKO bit = “0”
BCKO bit = “1”
tBCK
tBCK
dBCK
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
Duty Cycle
MS0557-E-02
2007/05
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
