欢迎访问ic37.com |
会员登录 免费注册
发布采购

AK4646 参数 Datasheet PDF下载

AK4646图片预览
型号: AK4646
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声编解码器与MIC / SPK- AMP [Stereo CODEC with MIC/SPK-AMP]
分类和应用: 解码器编解码器
文件页数/大小: 79 页 / 813 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
 浏览型号AK4646的Datasheet PDF文件第6页浏览型号AK4646的Datasheet PDF文件第7页浏览型号AK4646的Datasheet PDF文件第8页浏览型号AK4646的Datasheet PDF文件第9页浏览型号AK4646的Datasheet PDF文件第11页浏览型号AK4646的Datasheet PDF文件第12页浏览型号AK4646的Datasheet PDF文件第13页浏览型号AK4646的Datasheet PDF文件第14页  
[AK4646]  
Units  
min  
typ  
max  
Parameter  
Speaker-Amp Characteristics: DAC SPP/SPN pins, ALC=OFF,OVOL=0dB, CL=3μF, Rserial=10Ω x 2, BTL,  
SVDD=3.8V  
Output  
Voltage  
(Note 16)  
S/(N+D)  
(Note 17)  
-
-
6.33  
60  
-
-
Vpp  
dB  
SPKG1-0 bits = 11, -0.5dBFS  
SPKG1-0 bits = 11, -0.5dBFS  
S/N  
(A-weighted)  
-
50  
-
90  
-
-
-
-
3
dB  
Ω
μF  
Load Impedance (Note 18)  
Load Capacitance (Note 18)  
Mono Input: MIN pin (External Input Resistance=20kΩ)  
Maximum Input Voltage (Note 19)  
Gain (Note 20)  
-
1.98  
-
Vpp  
MIN Æ LOUT/ROUT  
-4.5  
0
+4.5  
dB  
dB  
dB  
dB  
LOVL1-0 bit = 00”  
LOVL1-0 bit = 01”  
LOVL1-0 bit = 10”  
LOVL1-0 bit = 11”  
-
-
-
+2  
+4  
+6  
-
-
-
MIN Æ SPP/SPN  
+0.1  
+4.6  
+6.6  
+8.6  
+10.6  
+6.6  
+8.6  
+9.1  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
ALC bit = 0, SPKG1-0 bits = 00”  
ALC bit = 0, SPKG1-0 bits = 01”  
ALC bit = 0, SPKG1-0 bits = 10”  
ALC bit = 0, SPKG1-0 bits = 11”  
ALC bit = 1, SPKG1-0 bits = 00”  
ALC bit = 1, SPKG1-0 bits = 01”  
ALC bit = 1, SPKG1-0 bits = 10”  
ALC bit = 1, SPKG1-0 bits = 11”  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+10.6  
+12.6  
Power Supplies:  
Power Up (PDN pin = H)  
All Circuit Power-up (Note 21)  
AVDD+DVDD  
-
-
15  
4
23  
12  
mA  
mA  
SVDD (No Output)  
Power Down (PDN pin = L) (Note 22)  
AVDD+DVDD+SVDD  
-
1
100  
μA  
Note 17. In case of measuring at SPP and SPN pins.  
Note 18. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 34. Load  
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be  
connected at both SPP and SPN pins, respectively.  
Note 19. Maximum voltage is in proportion to both AVDD and external input resistance (Rin).  
Vin = 0.636 x AVDD x Rin / 20kΩ (typ).  
Note 20. The gain is in inverse proportion to external input resistance  
Note 21. PLL Master Mode (MCKI=12MHz); PMADL = PMADR = PMDAC = PMLO = PMSPK = PMVCM = PMPLL  
= MCKO = PMBP = PMMP = M/S bits = 1. MPWR pin outputs 0mA.  
AVDD= 10mA(typ), DVDD=5mA(typ).  
EXT Slave Mode (PMPLL = M/S = MCKO bits = 0): AVDD=10mA(typ), DVDD=4mA(typ).  
Note 22. All digital input pins are fixed to DVDD or DVSS.  
MS0557-E-02  
2007/05  
- 10 -