ASAHI KASEI
[AK4645]
1/fCLK
VIH
VIL
MCKI
LRCK
tCLKH
tCLKL
1/fs
VIH
VIL
tLRCKH
tBCK
tLRCKL
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
VIL
BICK
tBCKH
tBCKL
tMCKL
fMCK
50%TVDD
MCKO
dMCK = tMCKL x fMCK x 100
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
50%TVDD
MSB
tSDH
tSDS
VIH
VIL
SDTI
MSB
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0543-E-00
2006/09
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