ASAHI KASEI
[AK4645]
Timing Diagram
1/fCLK
VIH
VIL
MCKI
tCLKH
tCLKL
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
1/fMCK
MCKO
50%TVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
Note 37. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%TVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%TVDD
50%TVDD
BICK
(BCKP = "1")
tBSD
SDTO
SDTI
50%TVDD
MSB
tSDS
tSDH
VIH
VIL
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0543-E-00
2006/09
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
