ASAHI KASEI
[AK4644]
Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
(Addr:01H, D1)
(3)
External MCKI
Input
Figure 83. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
(1)
PMPLL bit
(Addr:01H, D0)
BICK frequency: 64fs
(2)
External BICK
External LRCK
Input
Input
(1) Addr:01H, Data:00H
(2)
(2) Stop the external clocks
Figure 84. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
3. PLL Slave (MCKI pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
(1)
PMPLL bit
(Addr:01H, D0)
BICK frequency: 64fs
(1)
MCKO bit
(Addr:01H, D1)
(1) Addr:01H, Data:00H
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 85. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
MS0477-E-01
2006/10
- 92 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
