ASAHI KASEI
[AK4644]
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AK4644
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Revision History
Date (YY/MM/DD) Revision Reason
Page Contents
06/04/04
06/10/24
00
01
First Edition
Spec change
36
55
MIC/LINE Input Selector
“When full-differential input is used, the signal should
not be input to the pins marked by “X” in Table 21.”
was added.
Table 21 (Handling of MIC/Line Input Pins) was added.
Stereo Line Output Control Sequence
Power-down mode:
Error correct
PMLO bit = “1” Æ PMLO bit = “0”
63
73
I2C Bus Control Mode
“those most significant 3-bits are fixed to zeros”
Æ “those most significant 2-bits are fixed to zeros”
Register Definitions (Addr=0FH)
HPM bit: “When the HPM bit = “1”, (L+R)/2 signals
are output to Lch and Rch of the Headphone-Amp.
Both PMHPL and PMHPR bits should be “1” when
HPM bit is “1”.
Æ “When the HPM bit = “1”, DAC output signal is
output to Lch and Rch of the Headphone-Amp as
(L+R)/2.”
86
87
88
Control Sequence (Clock Setup: Ext Slave Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=01H Æ 00H
Control Sequence (Clock Setup: Ext Master Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=01H Æ 00H
Control Sequence (Mic Recording)
ALC Setting: “Refer to Figure 23” Æ “Refer to Figure 36”
MS0477-E-01
2006/10
- 95 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
