ASAHI KASEI
[AK4644]
Headphone-amp Output
Example:
PLL, Master Mode
FS3-0bits
0,000
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
1,111
10
(Addr:05H, D5&D2-0)
(1)
Bass Boost Level :Middle
DACH bit
(Addr:0FH, D0)
(2)
(13)
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(3) Addr:0EH, Data:19H
(4) Addr:09H&0CH, Data:91H
(5) Addr:0AH&0DH, Data:28H
(6) Addr:00H, Data:64H
(7) Addr:01H, Data:39H
(8) Addr:01H, Data:79H
Playback
BST1-0 bits
(Addr:0EH, D3-2)
00
00
(3)
(12)
IVL/R7-0bits
E1H
18H
91H
(Addr:09H&0CH, D7-0)
(4)
DVL/R7-0bits
28H
(Addr:0AH&0DH, D7-0)
(5)
PMDAC bit
(Addr:00H, D2)
(6)
(11)
PMMIN bit
(Addr:00H, D5)
(9) Addr:01H, Data:39H
(10) Addr:01H, Data:09H
(7)
(8)
(10)
PMHPL/Rbits
(Addr:01H, D5-4)
HPMTN bit
(Addr:01H, D6)
(9)
(11) Addr:00H, Data:40H
(12) Addr:0EH, Data:11H
(13) Addr:0FH, Data:08H
HPL/R pins
Normal Output
Figure 80. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4644 is PLL mode, DAC should be powered-up in
consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”
(3) Set up the low frequency boost level (BST1-0 bits)
(4) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”
Output voltage of headphone-amp is still HVSS.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
τ
r
= 100ms(typ), 250ms(max).
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
GND, the pop noise occurs. It takes twice of that the common voltage goes to GND.
τ
f
= 100ms(typ), 250ms(max).
τ
f
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0”
(12) Off the bass boost: BST1-0 bits = “00”
(13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
MS0477-E-01
2006/10
- 89 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
